The Quarky Engineer

I got a new office chair today. Perhaps more like a new chair office. So far I like the curved display.

A quick test of my mobile/remote internet setup. Starlink dish, v2, plus EcoFlow Delta Pro battery (3.6kWh capacity), plus a 100 watt solar panel.

The new version 2 dish draws 30-40 watts, so with no supplement the battery will give you over 3 days of internet, and the addition of the solar can extend that quite a bit. For unlimited run time I would probably need to use 2 of my 100w panels, and a bit more if it was party cloudy.

Not bad for a remote capable setup with almost 200mbit download speed.

A few cool things in the analog tool category. Always useful to be able to calculate yield from fireball size! The fallout map is an interesting overlay map for 250,000:1 and 50,000:1.

Something interested appeared. These are Soviet era radiation dosimeters. They are particularly interesting being they are electro-mechanical and resettable. They have a small quartz fiber inside that gets charged up and the exposure to radiation reduces that charge and moves the fiber. They could potentially work over a very long period of time.

The little included stand has a small movable coil that can ‘recharge’ the fiber and can set the start point.

Neat in that after the first person holding it dies from radiation exposure the next person can re use it!

The scale is – 0 – 500 rad. That is a pretty aggressive exposure scale for a dosimeter.

Time for some logic stuff….

I setup a Starlink as a backup internet connection at home. While my Comcast connection has been reliable from the perspective of the Comcast service side, it is not very reliable from the tree-ripping-down-a-pole side of things.

It was interesting that during setup the dish does some self alignment, and appears to favor a slightly north facing direction, which would appear to be a result of the orbital density being the highest in that direction.

It is relatively quick to setup, and downlink speed was over 200mb and latency in the 50ms range.

Hmm. April showers bring may flowers?

It is amazing how few options are left if you want to build/design your own 16-128 node multiprocessor retro-supercomputer. In terms of what is actually still in production and comes in a reasonable to solder (non BGA) package like a QFP:

Freescale MC68EC000 (68k architecture)
Some various x86 (386 and 486) varieties.
A number of Z80 variates
6502/65C816
A few ARM cores, although most are microcontrollers not standalone.

In some ways the best option is to implement one of the classics (like a MIPS R5000) on an FPGA ( of course that certainly isn’t in a QFP package )

Anything obvious I am missing? Also helpful if they are not crazy expensive, if building say a 64 or 128 node machine.

Success! After some more investigation, I have been successful at getting this 40 year old Televideo 1605H working. The path was a bit more circuitous than I would have liked. When I last debugged I had determined the memory failure look like any write to memory followed by a read from memory would return what was just written, even if reading a different address. That suggested something was amok with the address lines going to the DRAM. I did some digging around in the schematic and had a few candidate parts that could be the problem source.

One such part was a 74LS158 used to multiplex the row and column address from the address bus. There are 2 of them and they have 8 bits in and 4 bits out each, plus a select line. I put the logic analyzer on both the inputs and the outputs as well as the RAS and CAS line for that bank. Sure enough I could see the RAS and CAS lines active while the BIOS RAM test was executing. Looking closer I could see the output of the 158 was staying with just one set of address lines (the high ones), and not switching to the lower address lines during the CAS line assertion. No doubt this would result in memory all accessing the same location for each ROW bank of memory.

Since the 158 didn’t seem to be switching, I took a look at the S input which should be toggling between each input in sync with the CAS and RAS lines. No changes at all so I look at the schematic to see the source which was a signal called RAM_SELECT which comes from another IC U43. U43 is a ‘Delay Line’ part which delays the switching of the multiplexer just long enough for the ram chips to latch in the ROW address. The 5150 PC has a similar part in its design.

I look around the board to find U43, and I find the socket, but no IC! Sure enough there is a socket labeled U43, but nothing in it. With no IC, there is no way that select line would ever work, and no way the machine could have worked. It isn’t any easy part to replace because I have no idea what the delay spec is. Since this machine was supposed to be working, I start digging around in the rest of the machine. Sure enough buried inside the floppy drive is the IC, bouncing around. It must have come off the board during shipping and made its way into a nice hidden location. I noticed the empty socket before, but there are several others on the board for other expansion use case so I didn’t think anything of it.

After getting the part back to its home the machine POSTed right up and just needs to be reassembled. It was an interesting learning opportunity and I was happy that the debugging lead the the right part, albeit missing.

Next up is to completely disassembly the machine so I can retrobright the case.

Fun Times!

A bit more debugging on my non-working motherboard. Before I dig out the big and complicated logic analyzer I thought it would be good to take a crack with a simple USB based one. Only 16 channels, but enough to see some of the address bus and the CE/OE for the BIOS.

Sure enough, the BIOS is working and code is running, and the failure is the result of the initial 4K DRAM check failing. I did find the HLT instruction, and sure enough if the DRAM test subroutine fails it will execute the HLT. You can see the HLT at F773, and the DRAM test routine at F89D which returns (using a hard coded return address fixed up by loading SP before the call) setting zero flag if test was successful. It does a full write to the first 4K of memory with ‘AA’, but fails on the very first read (address 0).

I also checked the parallel port, and sure enough you can see the output status from the BIOS, which shows it not completing the first DRAM check. Interesting that it was in there but never mentioned anywhere.

I tested the DRAM, and replaced it with known good DRAM but no change, so there must be a problem with either the RAM decode or one of the buffers.

Next up I’ll setup capture on the DRAM buffer and see what is is reading/writing. And I may give that alternate bios a try which does more testing and display/speaker output, plus IO port 80 output.