I have found the implementation of full duplex asynchronous high speed comm channel over a very synchronous master only SPI bus to be an interesting challenge. This is for my CAN logging device that uses a PiZero connected to a dsPIC33 over SPI, and the dsPIC33 connected to two 1mbit CAN busses. Since the PI has to be the SPI master, it controls the rate and timing of when things can be ‘sent’ to it from the Pi. I implemented a GPIO signal from the PIC to the Pi to indicate the desire to transfer, and while that works, the desire to have that transfer independent of what is actually being sent in the other direction adds some challenge. On top of that to sustain the full SPI data rate while having both CAN busses receiving and transmitting at full rate requires the use of the TX and RX SPI FIFOs, which really adds some interesting complexity. Since the FIFOs need to be full before we know what is coming from the other side, it requires some padding and packet ‘encapsulation’. After many tweaks and tests, I was successful in transcribing a over 10 million packets at full rate with a 100% loaded CAN bus over the SPI bus as well as the second CAN bus without dropping anything, and with only a 20% padding rate. I think for the next rev I am going to switch up to a dsPIC with more memory (this one only has 8k of RAM), so I can afford a bit more buffering.

In practice this really is a worst case, as typically there would be filters in place so you are only logging things from data devices, and eliminating things like status and clocking traffic.