A bit more debugging on my non-working motherboard. Before I dig out the big and complicated logic analyzer I thought it would be good to take a crack with a simple USB based one. Only 16 channels, but enough to see some of the address bus and the CE/OE for the BIOS.

Sure enough, the BIOS is working and code is running, and the failure is the result of the initial 4K DRAM check failing. I did find the HLT instruction, and sure enough if the DRAM test subroutine fails it will execute the HLT. You can see the HLT at F773, and the DRAM test routine at F89D which returns (using a hard coded return address fixed up by loading SP before the call) setting zero flag if test was successful. It does a full write to the first 4K of memory with ‘AA’, but fails on the very first read (address 0).

I also checked the parallel port, and sure enough you can see the output status from the BIOS, which shows it not completing the first DRAM check. Interesting that it was in there but never mentioned anywhere.

I tested the DRAM, and replaced it with known good DRAM but no change, so there must be a problem with either the RAM decode or one of the buffers.

Next up I’ll setup capture on the DRAM buffer and see what is is reading/writing. And I may give that alternate bios a try which does more testing and display/speaker output, plus IO port 80 output.