I have been noodling around the idea of doing my own processor for my supercomputer. I’d like to play around with some old school SIMD PE architectures, and those design works well within an FPGA implementation. Curious if any of my nerd/processor architecture friends would comment on a selective execution idea I am considering.

http://www.sponaugle.com/papers/SIMDPartitionIdea.pdf

A classical problem in SIMD machines is how to handle partial execution, where you want only some processors in the cluster to execute certain instructions. The method I am proposing is a combination of an old school vector mask combined with RISC style register/register instruction set.
http://www.sponaugle.com/papers/SIMDPartitionIdea.pdf